Microprocessor的問題，透過圖書和論文來找解法和答案更準確安心。 我們找到下列懶人包和總整理

Mineralogy of Arizona, Fourth Edition

為了解決Microprocessor的問題，作者Grant, Raymond W.,Gibbs, Ron,Jong, Harvey 這樣論述：

Raymond W. Grant, co-author of the Mineralogy of Arizona, third edition, has a PhD in geology and has retired after teaching geology at Mesa Community College in Mesa, Arizona for 31 years. Ronald B. Gibbs has bachelor’s degrees in geology and mining engineering and has retired after a career in th

e copper mining industry. Harvey W. Jong received a bachelor’s degree from M.I.T. and a master’s degree from the University of California, Santa Barbara; both degrees are in electrical engineering. After working in the microprocessor industry for 15 years, he decided to pursue his passion for photo

graphy and started a digital media studio. Jan C. Rasmussen holds a PhD in economic geology from the University of Arizona and was the associate curator of the University of Arizona Mineral Museum and later the curator of the Arizona Mining and Mineral Museum in Phoenix. Stanley B. Keith has a Mas

ters degree in Geology from the University of Arizona and has worked for the Arizona Geological Survey before co-founding MagmaChem Exploration.

Microprocessor進入發燒排行的影片

以時序錯誤導向電軌調變技術實現之細緻化電壓調節及其於能耗可調數位系統之應用

為了解決Microprocessor的問題，作者陳威仁 這樣論述：

電壓調節技術(voltage scaling)在提高數位系統的能源效益方面具有相當大的潛力。然而，其節能效益在極大程度上受制於系統中穩壓電路之性能。本論文旨在提出一種可打破此限制的基於時序錯誤導向之電源軌調變技術，並以此技術實現細緻化的電壓調節。所提出之技術只需要少數電壓檔位，即可利用電源軌抖動(supply rail voltage dithering)的方式來近似出細緻化電壓調節的效果。因此，所提出之方法可以顯著降低晶片內穩壓電路的設計開銷。由於數位式低壓降線性穩壓器(digital low-dropout regulator, DLDO)具有無縫整合：（一）穩定輸出電壓、（二）電源軌抖

動、以及（三）電源閘控(power gating)等技術之特性，因此本論文利用DLDO來實現所提出之電源軌調變技術。為了精確與快速地實現適用於不同應用場景之DLDO電路，本論文也提出一種具有快速週轉時間的DLDO設計方法，並實際以一高性能DLDO設計為例驗證其效益。實驗結果指出，使用了聯電110奈米製程所製造的DLDO測試晶片展現出3毫伏特的超低漣波、67奈秒的輕載至重載暫態響應及250奈秒的重載至輕載暫態響應。與最先進的DLDO設計相比，該DLDO具有更簡潔的硬體架構且在品質因數(figure of merit)方面展現出高度競爭力。而後，本文以一種基於DLDO的抖動電源 (dithered

power supply)來實現所提出之電源軌調變技術。為了驗證所提出技術之效益，我們使用了一個具有時序錯誤偵測與修正能力之可程式化DSP資料路徑(datapath)作為測試載體。此測試晶片以台積電65奈米低功耗製程實現，而研究結果表明，所提出之電源軌調變技術有助於回收設計階段時留下之保守設計餘裕(design margin)並提高能源效率。量測結果指出，當該DSP資料路徑被程式化為一個無限脈衝響(infinite impulse response)數位濾波器以執行低通濾波時，所提技術之節能效益最高可達30.8%。最後，本論文將所提出之電源軌調變技術應用於即時影像處理系統中並探索其先天的容錯

能力。我們利用人眼視覺可將視訊中相鄰影格及影格中鄰近畫素進行視覺積分的特性，來達到即使不須對時序錯誤進行主動偵測及修正也能維持一定視覺品質的效果。因此，藉由巧妙安排容許時序錯誤發生之位置（藉由降低操作電壓），因時序錯誤所產生的錯誤畫素即可主動被人眼濾除。 該測試晶片以聯電40奈米製程實現，其搭載了一個即時視訊縮放引擎作為測試載具。在實驗結果中，該測試晶片展現了高達35%的節能效益，並能在不需對時序錯誤做出任何修正、且不須更動資料路徑架構的狀況下，仍能維持良好的主觀視覺感受。在五分制的平均主觀意見分數(mean opinion score)評量中，各類型的畫面皆達4分以上。而在客觀評量方面，峰值

信號雜訊比(peak signal-to-noise ratio)皆高於30分貝。

Compiler Design: Code Generation and Machine-level Optimization

為了解決Microprocessor的問題，作者Hack, Sebastian/ Wilhelm, Reinhard/ Seidl, Helmut 這樣論述：

While compilers for high-level programming languages are large complex software systems, they have particular characteristics that differentiate them from other software systems. Their functionality is almost completely well-defined - ideally there exist complete precise descriptions of the source a

nd target languages. Additional descriptions of the interfaces to the operating system, programming system and programming environment, and to other compilers and libraries are often available.The final stage of a compiler is generating efficient code for the target microprocessor. The applied techn

iques are different from usual compiler optimizations because code generation has to take into account the resource constraints of the processor - it has a limited number of registers, functional units, instruction decoders, and so on. The efficiency of the generated code significantly depends on th

e algorithms used to map the program to the processor, however these algorithms themselves depend not only on the target processor but also on several design decisions in the compiler itself - e.g., the program representation used in machine-independent optimization. In this book, the authors discus

s classical code generation approaches that are well suited to existing compiler infrastructures, and they also present new algorithms based on state-of-the-art program representations as used in modern compilers and virtual machines using just-in-time compilation.This book is intended for students

of computer science. The book is supported throughout with examples, exercises and program fragments. The authors are among the established experts on compiler construction, with decades of related teaching experience. Prof. Dr. Reinhard Wilhelm is the head of the Compiler Design Lab of the Univer

sität des Saarlandes, and his main research interests include compiler construction; Prof. Dr. Helmut Seidl heads the Institut für Informatik of the Technische Universität München, and his main research interests include automatic program analysis and the design and implementation of programming lan

guages; Dr. Sebastian Hack is a Junior Professor in the Computer Science Programming Group of the Universität des Saarlandes, and his main research areas include compilers and code generation.

基於分散式穩壓器的電源分配網路之電壓壓降降低技術

為了解決Microprocessor的問題，作者甘博方 這樣論述：

隨著科技越來越發達，生活中越來越多電子產品，其中攜帶式產品更是多不勝數，若想增加攜帶式產品的使用時間，勢必要想辦法降低功耗，最直接的方法便是降低操作電壓。隨著操作電壓下降，電壓在傳遞過程中造成的壓降變成不可忽視的一大問題，後端負載電路有可能因為傳遞過程中導致的操作電壓降低而產生不可預期的錯誤，在電源分配網路越大的晶片中此問題更為明顯。本論文主要針對上述提到的操作電壓在傳遞過程中造成的壓降進行改善，在電源分配網路中放置數顆數位低壓降穩壓器，再將數位低壓降穩壓器彼此間的資訊共享加速穩壓速度，最後將各點輸出電壓穩定在理想電壓的±5%之內。此外，將多顆穩壓器放入電源分配網路中，在負載不平衡的情況下，

容易造成電壓互相拉扯、不穩定的問題。利用本論文提出的架構能有效改善因負載不平衡造成的電壓不穩定現象。本論文使用UNC40nm製程進行分析、模擬及驗證，實驗結果顯示能有效改善電壓壓降，將輸出電壓穩定在理想輸出電壓值的±5%內。並且因為每個數位低壓降穩壓器在穩壓過程中知道彼此的資訊，所以能避免電壓拉扯的現象發生。